In Publicaciones

19 publicaciones relativas a diseño de carreteras están disponibles de forma gratuita a través del TRR (Transport Research Record). Los títulos de las comunicaciones son los siguientes:

  • Enhanced Design Guidelines for Interchange Loop Ramps (link)
  • Impact of Geometric Factors on the Capacity of Single-Lane Roundabouts (link)
  • A Practical Approach for the Estimation of Strength and Resilient Properties of Cementitious Materials (link)
  • Soil–Geosynthetic Interface Shear in Different Testing Scales (link)
  • Improving Pathways to Fixed-Route Transit: Transit Agency Practices to Expand Access for All Users (link)
  • Local Calibration of the MEPDG Distress and Performance Models for Ontario’s Flexible Roads: Overview, Impacts, and Reflection (link)
  • Identification and Calculation of Horizontal Curves for Low-Volume Roadways Using Smartphone Sensors (link)
  • Development of a Standardized Buttress for Approach Guardrail Transitions (link)
  • Adaptation Planning to Mitigate Coastal-Road Pavement Damage from Groundwater Rise Caused by Sea-Level Rise (link)
  • Before–After Evaluation of the Realignment of Horizontal Curves on Rural Two-Lane Roads (link)
  • Evaluating the Safety Effects of Span Wire to Mast Arm Signal Conversion (link)
  • Human Personality Based Investigation on Distance Threshold for Freeway Landscape Pattern (link)
  • A Model of the Probability of a Cross-Median Crash When a Vehicle Fully Crosses the Median (link)
  • First Application of UHPC Bridge Deck Overlay in North America (link)
  • Perceived Safety and Separated Bike Lanes in the Midwest: Results from a Roadway Design Survey in Michigan (link)
  • Performance of Skew Reinforcing in Inverted-T Bridge Caps (link)
  • Development of Live Load Model for Strength II Limit State in AASHTO LRFD Design Specifications (link)
  • Development of Transition between Free-Standing and Reduced-Deflection Portable Concrete Barriers (link)
  • Evaluation of Using Line Laser Scanner to Improve the Measurement of Average Least Dimension in Chip Seal Design Methods (link)



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